ICS1894-40 Datasheet, PDF (3/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
Pin
Name
AMDIX
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
13
MDIO
14
MDC
15
VDDIO
16
HWSW/
CRS
17
Regpin/
COL
18
AMDIX/RXD3
19
P3/RXD2
20
RXTRI/
RXD1
21
SI/LED4
22
FDPX/
RXD0
23
RMII/RXDV
24
SPEED
25
TXER
26
ANSEL/
RXCLK9
27
NOD/
RXER
Pin
Type
Pin Description
IN/Ipu AMDIX Enable
AIO Twisted pair port A (for either transmit or receive) positive signal
AIO Twisted pair port A (for either transmit or receive) negative signal
Ground Connect to ground.
Power 3.3V Power Supply
AIO Twisted pair port B (for either transmit or receive) negative signal
AIO Twisted pair port B (for either transmit or receive) positive signal
Power 3.3V Power Supply
AIO Transmit Current bias pin, connected to Vdd and ground via two resistors.
Ground Connect to ground.
Input Hardware reset for the whole chip (active low)
IO/Ipd PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
IO Management Data Input/Output
Input Management Data Clock
Power 3.3 V IO Power Supply.
IO/Ipu Hard pin select enable as input (during power on reset and hardware reset) and
MII CRS as output
IO/Ipd Full register access enable as input (during power on reset and hardware reset) and
MII COL output
IO/Ipu AMDIX enable as input (during power on reset and hardware reset)
Receive data Bit 3 for MII
IO/Ipd PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 for MII as output.
IO/Ipu RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 for both RMII and MII
IO/Ipd MII/SI mode select as input (during power on reset and hardware reset) and
LED # 4 as output
IO/Ipu Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 for both RMII and MII
IO/Ipd RMII/MII select as input (during power on reset and hardware reset)
Receive data valid for MII and CRS_DV for RMII as output
Ipd 10/100M input select. 1 = 100M mode, 0 = 10M mode.
IN TXER Input
IO/Ipu Auto-negotiation enable(during power on reset and hardware reset)
Receive clock MII
IO/Ipd Node/repeater select (during power on reset and hardware reset)
Receive error
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3
ICS1894-40 REV C 092909