954226 Datasheet, PDF (5/22 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Mobile P4TM Systems

954226
Programmable Timing Control Hub^TM for Mobile P4^TM Systems
MLF Pin Description (Continued)
PIN #
PIN NAME
29 CPUCLKC2_ITP/PCIEXC6
30 CPUCLKT2_ITP/PCIEXT6
31 VDDA
32 GNDA
33 IREF
34 CPUCLKC1
35 CPUCLKT1
36 VDDCPU
37 CPUCLKC0
38 CPUCLKT0
39 GND
40 SCLK
41 SDATA
42 VDDREF
43 X2
44 X1
45 GND
46 REF0
47 REF1/FSLC/TEST_SEL
48 CPU_STOP#
49 PCI/SRC_STOP#
50 PCICLK2/REQ_SEL**
51 VDDPCI
52 GND
53 PCICLK3
54 PCICLK4
55 PCICLK5
56 GND
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
I/O
IN
IN
I/O
PWR
PWR
OUT
OUT
OUT
PWR
DESCRIPTION
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
IDT^® Programmable Timing Control Hub^TM for Mobile P4^TM Systems
5
0930A—04/13/10