954226 Datasheet, PDF (15/22 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Mobile P4TM Systems

954226
Programmable Timing Control Hub^TM for Mobile P4^TM Systems
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDDA
-
3.3V Logic Input Supply _VDD
-
Voltage
Storage Temperature
Ts
-
Ambient Operating Temp Tambient
-
Junction Temperature
Tj
-
Input ESD protection HBM ESD prot
-
1_{Guaranteed by design and characterization, not 100% tested in production.}
-65
0
2000
4.6
V
4.6
V
150
°_C
70
°C
125
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN TYP MAX UNITS
Input High Voltage
V_IH
3.3 V +/-5%
2
V_DD +
V
0.3
Input Low Voltage
V_IL
3.3 V +/-5%
V_SS - 0.3
0.8
V
Input High Current
I_IH
V_IN = V_DD
-5
5
uA
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
-5
uA
Low Threshold Input-
High Voltage
I_IL2
V_{IH_FSL}
V_IN = 0 V; Inputs with pull-up resistors
3.3 V +/-5%
-200
0.7
uA
1.7
V
Low Threshold Input-
Low Voltage
V_{IL_FSL}
3.3 V +/-5%
V_SS - 0.3
0.35
V
Operating Supply Current
Powerdown Current
I_DD3.3OP
I_DD3.3PD
Full Active, C_L = Full load;
all diff pairs driven
all differential pairs tri-stated
400
mA
70
mA
12
mA
Input Frequency
F_i
V_DD = 3.3 V
14.31818
MHz
Pin Inductance
L_pin
7
nH
Input Capacitance
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
6
pF
C_INX
X1 & X2 pins
5
pF
Clk Stabilization
T_STAB
From V_DD Power-Up or de-assertion of
PD# to 1st clock
1.8
ms
Modulation Frequency
Triangular Modulation
30
33
kHz
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
Tfall_Pd#
PD# fall time of
5
ns
Trise_Pd#
PD# rise time of
5
ns
SMBus Voltage
V_DD
2.7
5.5
V
Low-level Output Voltage V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
0.4
V
mA
1000
ns
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.}
IDT^® Programmable Timing Control Hub^TM for Mobile P4^TM Systems
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0930A—04/13/10
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