954226 Datasheet, PDF (3/22 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Mobile P4TM Systems

954226
Programmable Timing Control Hub^TM for Mobile P4^TM Systems
TSSOP Pin Description (cont.)
PIN #
29 GND
30 PCIEXC4
31 PCIEXT4
PIN NAME
TYPE
PWR
OUT
OUT
32 PEREQ2#*/PCIEXC5
I/O
33 PEREQ1#*/PCIEXT5
34 VDDPCIEX
35 CPUCLKC2_ITP/PCIEXC6
I/O
PWR
OUT
36 CPUCLKT2_ITP/PCIEXT6
37 VDDA
38 GNDA
39 IREF
OUT
PWR
PWR
OUT
40 CPUCLKC1
41 CPUCLKT1
42 VDDCPU
43 CPUCLKC0
44 CPUCLKT0
45 GND
46 SCLK
47 SDATA
48 VDDREF
49 X2
50 X1
51 GND
52 REF0
53 REF1/FSLC/TEST_SEL
54 CPU_STOP#
55 PCI/SRC_STOP#
56 PCICLK2/REQ_SEL**
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
I/O
IN
IN
I/O
DESCRIPTION
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
IDT^® Programmable Timing Control Hub^TM for Mobile P4^TM Systems
3
0930A—04/13/10