954226 Datasheet, PDF (1/22 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Mobile P4TM Systems

DATASHEET
Programmable Timing Control Hub^TM for Mobile P4^TM
Systems
954226
Recommended Application:
CK410M Compatible Main Clock
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• PCI Express outputs cycle-cycle jitter < 125ps
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 4 - 0.7V current-mode differential PCI Express* pairs
• 1 - 0.7V current-mode differential CPU/PCI Express
selectable pair
• 1 - 0.7V current-mode differential SATA pair
• 1 - 0.7V current-mode differential LCDCLK/PCI Express
selectable pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 2 - REF, 14.318MHz
• SATA outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU, PCI Express
and SATA clocks
• +/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI Express
• Supports programmable spread percentage and
frequency
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, PCI Express pair
in PD for power management.
• PEREQ# pins to support PCI Express and SATA power
management.
MLF Pin Configuration
TSSOP Pin Configuration
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VDDPCI 1
ITP_EN/PCICLK_F0 2
**SELPCIEX_LCDCLK#/PCICLK_F1 3
42 VDDREF
41 SDATA
40 SCLK
Vtt_PwrGd#/PD 4
39 GND
VDD48 5
38 CPUCLKT0
FSLA/USB_48MHz 6
37 CPUCLKC0
GND 7
DOTT_96MHz 8
ICS 954226AKLF
36 VDDCPU
35 CPUCLKT1
DOTC_96MHz 9
34 CPUCLKC1
FSLB/TEST_MODE 10
33 IREF
LCDCLK_SS/PCIEXT0 11
32 GNDA
LCDCLK_SS/PCIEXC0 12
31 VDDA
PCIEXT1 13
30 CPUCLKT2_ITP/PCIEXT6
PCIEXC1 14
29 CPUCLKC2_ITP/PCIEXC6
15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
56 PCICLK2/REQ_SEL**
55 PCI/SRC_STOP#
54 CPU_STOP#
53 REF1/FSLC/TEST_SEL
52 REF0
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
**SELPCIEX_LCDCLK#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FSLA/USB_48MHz 12
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
FSLB/TEST_MODE 16
LCDCLK_SS/PCIEX0T 17
LCDCLK_SS/PCIEX0C 18
PCIEXT1 19
PCIEXC1 20
VDDPCIEX 21
PCIEXT2 22
PCIEXC2 23
PCIEXT3 24
PCIEXC3 25
SATACLKT 26
SATACLKC 27
VDDPCIEX 28
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/PCIEXT6
35 CPUCLKC2_ITP/PCIEXC6
34 VDDPCIEX
33 PEREQ1#*/PCIEXT5
32 PEREQ2#*/PCIEXC5
31 PCIEXT4
30 PCIEXC4
29 GND
56-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Table 1: Frequency Selection Table
FSLC B6b2 FSLB B6b1 FSLA B6b0
CPU
MHz
0
0
0
266.66
PCIEX
MHz
100.00
PCI REF
MHz MHz
33.33 14.318
USB
MHz
48.00
0
0
1
133.33 100.00 33.33 14.318 48.00
0
1
0
200.00 100.00 33.33 14.318 48.00
0
1
1
166.66 100.00 33.33 14.318 48.00
1
0
0
333.33 100.00 33.33 14.318 48.00
1
0
1
100.00 100.00 33.33 14.318 48.00
1
1
0
400.00 100.00 33.33 14.318 48.00
1
1
1
200.00 100.00 33.33 14.318 48.00
IDT^® Programmable Timing Control Hub^TM for Mobile P4^TM Systems
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
Spread %
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0930A—04/13/10
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