954226 Datasheet, PDF (4/22 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Mobile P4TM Systems

954226
Programmable Timing Control Hub^TM for Mobile P4^TM Systems
MLF Pin Description
PIN #
1 VDDPCI
PIN NAME
2 ITP_EN/PCICLK_F0
3 **SELPCIEX_LCDCLK#/PCICLK_F1
4 Vtt_PwrGd#/PD
5 VDD48
6 FSLA/USB_48MHz
7 GND
8 DOTT_96MHz
9 DOTC_96MHz
10 FSLB/TEST_MODE
11 LCDCLK_SS/PCIEXT0
12 LCDCLK_SS/PCIEXC0
13 PCIEXT1
14 PCIEXC1
15 VDDPCIEX
16 PCIEXT2
17 PCIEXC2
18 PCIEXT3
19 PCIEXC3
20 SATACLKT
21 SATACLKC
22 VDDPCIEX
23 GND
24 PCIEXC4
25 PCIEXT4
26 PEREQ2#*/PCIEXC5
27 PEREQ1#*/PCIEXT5
28 VDDPCIEX
TYPE
PWR
I/O
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
IDT^® Programmable Timing Control Hub^TM for Mobile P4^TM Systems
4
0930A—04/13/10