ICS841N254I Datasheet, PDF (3/23 Pages) Integrated Device Technology – FEMTOCLOCK® NG Crystal-to-LVDS/HCSL Clock Synthesizer

ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Function Tables
Table 3A. Output Divider and Output Frequency
Inputs
F_SEL1
F_SEL0
Operation
0 (default)
0
1
1
0 (default)
1
0
1
f_OUT = f_REF * 25 ÷ 4
f_OUT = f_REF * 5
f_OUT = f_REF * 4
f_OUT = f_REF * 10
NOTE: F_SEL[1:0] are asynchronous controls.
f_OUT with f_REF = 25MHz
156.25MHz
125MHz
100MHz
250MHz
Table 3B. PLL Reference Clock Select Function Table
Input
REF_SEL
Operation
0 (default)
The crystal interface is selected as reference clock
1
The REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
Table 3C. PLL BYPASS Function Table
Input
BYPASS
Operation
0 (default)
PLL is enabled. The reference frequency f_REF is multiplied by the PLL
feedback divider of 25 and then divided by the selected output divider N.
1
PLL is bypassed. The reference frequency f_REF is divided by the selected
output divider N. AC specifications do not apply in PLL bypass mode.
NOTE: BYPASS is an asynchronous control.
Table 3D. nOEA Output Enable Function Table
Input
nOEA
Operation
0 (default)
QA0, nQA0 and QA1, nQA1 outputs are enabled
1
QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
NOTE: nOEA is an asynchronous control.
Table 3E. nOEB Output Enable Function Table
Input
nOEB
Operation
0 (default)
QB0, nQB0 and QB1, nQB1 outputs are enabled
1
QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
NOTE: nOEB is an asynchronous control.
ICS841N254AKI REVISION A APRIL 18, 2011
3
©2011 Integrated Device Technology, Inc.