ICS841N254I Datasheet, PDF (17/23 Pages) Integrated Device Technology – FEMTOCLOCK® NG Crystal-to-LVDS/HCSL Clock Synthesizer

ICS841N254I Data Sheet
Schematic Layout
Figure 6 shows an example of ICS41N254I application schematic. In
this example, the device is operated at V_DD= V_DDOA = V_DDOB = 3.3V.
A 12pF parallel resonant 25MHz crystal is used. The load
capacitance C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. Depending on the parasitics of the printed circuit board
layout, these values might require a slight adjustment to optimize the
frequency accuracy. Crystals with other load capacitance
specifications can be used. This will requiring adjusting C1 and C2.
For this device, the crystal load capacitors are required for proper
opteration.
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS841N254I provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
C6
0.1u
VDD
R3
10
VDDA
C3
C7
0.01u
10u
VDD
VDD
C4
0.1u
Q1
Ro ~ 7 Ohm R8 Zo = 50 Ohm
43
VDD
Driv er_LVCMOS
REF_CLK
nOEA
C5
0.1u
U1
1
2
3
4
VDD
nc
VDDA
5
6
7
nc
GND
REF_CLK
8
nOEA
VDD
R4 33
QB0
Zo = 50
+
TL2
R5 33
nQB0
Zo = 50
-
TL3
R6 R7
Using for PCI Express
VDDO
50 50
Add-In Card
R2
475
VDD=3.3V
VDDOA= VDDOB=3.3V
HCSL Termination
IREF
GND
nQA0
24
23
22
21
QA0
VDDOA
nQA1
20
19
18
QA1
GND
17
Optional
R9 33
QB1
QB1_33 Zo = 50
+
nQA0
VDDO
R10 33
TL5
QA0
nQB1
nQB1_33 Zo = 50
-
TL6
R11 R12
50 50
LVDS Termination
Using for PCI Express
Point-to-Point
Connection
X1
C1
25MHz
XTAL_IN
VDD
5pF
12pF
XTAL_OUT
C8
C2
0.1u
5pF
QA1
+
Zo = 100 Ohm Dif f erential R1
100
nQA1
-
3.3V
BLM18BB221SN1
1
2
Ferrite Bead C10
C11 C17
C9
0.1uF
10uF 0.1uF 0.1uF
VDDO
3.3V
BLM18BB221SN1
1
2
VDD
Ferrite Bead C13
C14
C12
0.1uF
10uF 0.1uF
Figure 6. ICS841N254I Application Schematic
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
ICS841N254AKI REVISION A APRIL 18, 2011
17
©2011 Integrated Device Technology, Inc.