ICS841N254I Datasheet, PDF (1/23 Pages) Integrated Device Technology – FEMTOCLOCK® NG Crystal-to-LVDS/HCSL Clock Synthesizer

FEMTOCLOCK^® NG
Crystal-to-LVDS/HCSL Clock Synthesizer
ICS841N254I
DATA SHEET
General Description
The ICS841N254I is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates four
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with excellent phase jitter performance. The four outputs
are organized in two banks of two LVDS and two HCSL ouputs.The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The synthesized clock frequency and
the phase-noise performance are optimized for driving RIO 1.3 and
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V
voltage supplies and is packaged in a small 32-lead VFQFN
package. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Function Table
Inputs
F_SEL1
F_SEL0
0 (default)
0 (default)
0
1
1
0
1
1
Output Frequency with
f_XTAL = 25MHz
156.25MHz
125MHz
100MHz
250MHz
NOTE: F_SEL[1:0] are asynchronous controls.
Block Diagram
Features
• Fourth generation FemtoClock® (NG) technology
• Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
• Four differential clock outputs (two LVDS and two HCSL outputs)
• Crystal interface designed for 25MHz,
parallel resonant crystal
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
• Power supply noise rejection PSNR: -50dB (typical)
• LVCMOS interface levels for the frequency select input
• Full 3.3V or 2.5V supply voltage
• Available in both standard (RoHS 5) and Lead-free (RoHS 6)
packages
• -40°C to 85°C ambient operating temperature
Pin Assignment
32 31 30 29 28 27 26 25
VDD 1
24 IREF
nc 2
ICS841N254I
23 GND
VDDA 3
nc 4
32-lead VFQFN
K Package
22 nQA0
21 ^QA0
GND 5 ^{5mm x 5mm x 0.925mm} 20 VDDOA
package body
REF_CLK 6
Top View
19 nQA1
nOEA 7
18 QA1
VDD 8
17 GND
9 10 11 12 13 14 15 16
XTAL_IN
XTAL_OUT
REF_CLK
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
nOEB
IREF
OSC ₀
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
1
2
PFD
&
LPF
FemtoClock® NG
VCO
625MHz
1
÷N
0
÷25
QA0 _LVDS
nQA0
QA1 _LVDS
nQA1
QB0 _HCSL
nQB0
QB1 _HCSL
nQB1
ICS841N254AKI REVISION A APRIL 18, 2011
1
©2011 Integrated Device Technology, Inc.