8413S12B Datasheet, PDF (3/33 Pages) Integrated Device Technology – HCSL/ LVCMOS Clock Generator

8413S12B Datasheet.
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 18, 38
2,
3
4,
5
6,
7
8,
9
10,
12
11
13, 16, 19,
36, 37, 54,
55, 72
14,
15
Name
GND
FSEL_A0.
FSEL_A1
FSEL_B0,
FSEL_B1
FSEL_C0,
FSEL_C1
FSEL_D0,
FSEL_D1
FSEL_E0,
FSEL_E1
V_DDA
nc
XTAL_IN,
XTAL_OUT
Type
Power
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Power
Pulldown
Description
Power supply ground.
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QDx, nQDx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QEx, nQEx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Unused
No connect.
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
17
20, 39, 53
21
REF_SEL
V_DD
PLL_SEL
Input
Power
Input
Pullup
Pullup
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
22
CLK
Input
Pulldown Non-inverting differential clock input.
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
nCLK
OE_A
V_{DDO_A}
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
V_{DDO_B}
OE_C
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Pullup/
Pulldown
Pullup
Pullup
Pullup
Inverting differential clock input. Internal resistor bias to V_DD/2.
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
41, 42
QC0, nQC0
Output
Differential output pair. HCSL interface levels.
43, 44
QC1, nQC1
Output
Differential output pair. HCSL interface levels.
45
46
47, 48
V_{DDO_C}
V_{DDO_D}
QD0, nQD0
Power
Power
Output
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
Differential output pair. HCSL interface levels.
49, 50
QD1, nQD1
Output
Differential output pair. HCSL interface levels.
©2016 Integrated Device Technology, Inc.
3
Revision E, August 18, 2016