8413S12B Datasheet, PDF (1/33 Pages) Integrated Device Technology – HCSL/ LVCMOS Clock Generator

HCSL/ LVCMOS Clock Generator
8413S12B
General Description
The 8413S12B is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12B supports telecommunication,
networking, and storage requirements.
Applications
• CPE Gateway Design
• Home Media Servers
• 802.11n AP or Gateway
• Soho Secure Gateway
• Soho SME Gateway
• Wireless Soho and SME VPN Solutions
• Wired and Wireless Network Security
• Web Servers and Exchange Servers
Pin Assignment
Features
• Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
• One single-ended QG LVCMOS/LVTTL clock output at 125MHz
• One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15 output impedance
• Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15 output impedance
• Selectable external crystal or differential (single-ended) input
source
• Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
• Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
• Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
• -40°C to 85°C ambient operating temperature
• Available in Lead-free (RoHS 6) package
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
V_DDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
54
2
53
3
52
4
51
5
50
6
;;;;;;
49
7
48
8
47
9
10
6
46
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
V_DD
IREF
OE_D
nQD1
QD1
nQD0
QD0
V_{DDO_D}
V_{DDO_C}
nQC1
QC1
nQC0
QC0
OE_C
V_DD
GND
nc
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©2016 Integrated Device Technology, Inc.
1
Revision E, August 18, 2016