8413S12B Datasheet, PDF (13/33 Pages) Integrated Device Technology – HCSL/ LVCMOS Clock Generator

Typical Phase Noise at 156.25MHz
8413S12B Datasheet.
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.60ps (typical)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
13
Revision E, August 18, 2016