8413S12B Datasheet, PDF (27/33 Pages) Integrated Device Technology – HCSL/ LVCMOS Clock Generator

8413S12B Datasheet.
Power Considerations
This section provides information on power dissipation and junction temperature for the 8413S12B. Equations and example calculations are
also provided.
1. Power Dissipation.
The total power dissipation for the 8413S12B is the sum of the core power plus the output power dissipated due to the loading.
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to the loading.
• Power (core)_MAX = V_{DD_MAX} * (I_DD + I_DDA)= 3.465V * (103mA + 16mA) = 412.3mW
• Power (HCSL)_MAX = (3.465V – 17mA * 50) 17mA = 44.5mW per output
• Total Power (HCSL)_MAX = 44.5mW * 10 = 445mW
LVCMOS Driver Power Dissipation
• Output Impedance R_OUT Power Dissipation due to Loading 50 to V_DD/2
Output Current I_OUT = V_{DD_MAX} / [2 * (50 + R_OUT)] = 3.465V / [2 * (50 + 15)] = 27mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (LVCMOS) = R_OUT * (I_OUT)² = 15 * (27mA)² = 11mW per output
• Total Power Dissipation on the R_OUT
Total Power (R_OUT) = 11mW * 4 = 44mW
Total Power Dissipation
• Total Power
= Power (core) + Total Power (HCSL) + Total Power (R_OUT)
= 412.3mW + 445mW + 44mW
= 901.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 25.4°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.901W * 25.4°C/W = 108°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 9. Thermal Resistance _JA for 72 Lead VFQFN, Forced Convection
_JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
25.4°C/W
1
20.5°C/W
2.5
18.4°C/W
©2016 Integrated Device Technology, Inc.
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Revision E, August 18, 2016