83905 Datasheet, PDF (17/21 Pages) Integrated Device Technology – Low Skew, 1:6 Crystal-to-LVCMOS/ LVTTL Fanout Buffer

83905 Datasheet
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Package Outline - M Suffix for 16-Lead SOIC
Table 9A. Package Dimensions for 16-Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75

0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
150 il (N
B d ) SOIC
Table 9B. Package Dimensions for 16-Lead SOIC
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
9.80
10.00
E
3.80
4.00
e
1.27 Basic
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27

0°
8°
Reference Document: JEDEC Publication 95, MS-012
©2016 Integrated Device Technology, Inc.
17
Revision D September 27, 2016