83905 Datasheet, PDF (14/21 Pages) Integrated Device Technology – Low Skew, 1:6 Crystal-to-LVCMOS/ LVTTL Fanout Buffer

83905 Datasheet
Layout Guideline
Figure 5 shows an example of 83905 application schematic. The
schematic example focuses on functional connections and is not
configuration specific. In this example, the device is operated at
V_DD = 3.3V and V_DDO = 1.8V. The crystal inputs are loaded with an
18pf load resonant quartz crystal. The tuning capacitors (C1, C2)
are fairly accurate, but minor adjustments might be required. Refer
to the pin description and functional tables in the datasheet to
ensure the logic control inputs are properly set. For the LVCMOS
output drivers, two termination examples are shown in the
schematic. For additional termination examples are shown in the
LVCMOS Termination Application Note.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 83905
provides separate V_DD and V_DDO power supplies to isolate any
high switching noise from coupling into the internal oscillator. In
order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to
the power pins as possible. This is represented by the placement
of these capacitors in the schematic. If space is limited, the ferrite
beads, 10uF and 0.1uF capacitor connected to the board supplies
can be placed on the opposite side of the PCB. If space permits,
place all filter components on the device side of the board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices.
The filter performance is designed for a wide range of noise
frequencies. This low-pass filter starts to attenuate noise at
approximately 0kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
Figure 5. Schematic of Recommended Layout
©2016 Integrated Device Technology, Inc.
14
Revision D September 27, 2016