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| 83905 Datasheet, PDF (15/21 Pages) Integrated Device Technology – Low Skew, 1:6 Crystal-to-LVCMOS/ LVTTL Fanout Buffer | |||
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83905 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 83905.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 83905 is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
⢠Power (core)MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(10mA + 5mA) = 51.9mW
⢠Output Impedance ROUT Power Dissipation due to Loading 50ï to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50ï + ROUT)] = 3.465V / [2 * (50ï + 7ï)] = 30.4mA
⢠Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 7ï * (30.4mA)2 = 6.5mW per output
⢠Total Power Dissipation on the ROUT
Total Power (ROUT) = 6.5mW * 6 = 39mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDD)2 = 19pF * 25MHz * (3.465V)2 = 5.70mW per output
Total Power (25MHz) = 5.70mW * 6 = 34.2mW
Total Power Dissipation
⢠Total Power
= Power (core)MAX + Total Power (ROUT) + Total Power (25MHz)
= 51.98mW + 39mW + 34.2mW
= 125.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj = ï±JA * Pd_total + TA
Tj = Junction Temperature
ï±JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ï±JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.125W *100.3°C/W = 82.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Table 7. Thermal Resistance ï±JA for 16-Lead TSSOP, Forced Convection
ï±JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
1
96.0°C/W
2.5
93.9°C/W
©2016 Integrated Device Technology, Inc.
15
Revision D September 27, 2016
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