ICS9LPRS436CKILF Datasheet, PDF (16/20 Pages) Integrated Device Technology – Low Power Clock for Intel Atom®-Based Systems

ICS9LPRS436C
Low Power Clock for Intel Atom^®-Based Systems
SMBus Table: CPU/SRC/PCI PLL Frequency Control Register
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function
N Divider Prog bit 2
N Divider Prog bit 1
M Divider Programming
bit (5:0)
Type
0
1
PWD
RW
X
RW The decimal representation of M and N
X
RW Divider in Byte 11 and 12 will configure the X
RW CPU PLL VCO frequency. Default at
X
RW power up = latch-in or Byte 0 ROM table. X
RW
VCO Frequency = 50 x
X
RW
Ndiv(10:0)/Mdiv(5:0)
X
RW
X
SMBus Table: CPU/SRC/PCI PLL Frequency Control Register
Byte 12
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
N Divider Programming Byte12
bit(7:0) and Byte11 bit(7:6)
Type
0
1
RW
RW The decimal representation of M and N
RW Divider in Byte 11 and 12 will configure the
RW CPU PLL VCO frequency. Default at
RW power up = latch-in or Byte 0 ROM table.
RW
VCO Frequency = 50 x
RW
Ndiv(10:0)/Mdiv(5:0)
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU/SRC/PCI PLL Frequency Control Register
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
Type
0
1
PWD
RW
X
RW
X
Spread Spectrum Programming
bit(7:0)
RW
RW
RW
RW
These Spread Spectrum bits in Byte 13
and 14 will program the spread percentage
of CPU PLL
X
X
X
X
RW
X
RW
X
SMBus Table: CPU/SRC/PCI PLL Frequency Control Register
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Type
0
1
PWD
RW
0
RW
X
Spread Spectrum Programming
bit(15:8)
RW
RW
RW
RW
These Spread Spectrum bits in Byte 13
and 14 will program the spread percentage
of CPU PLL
X
X
X
X
RW
X
RW
X
Bytes [15:22] Are reserved
IDT^® Low Power Clock for Intel Atom^®-Based Systems
16
1561A — 06/01/10