ICS9LPRS436CKILF Datasheet, PDF (15/20 Pages) Integrated Device Technology – Low Power Clock for Intel Atom®-Based Systems

ICS9LPRS436C
Low Power Clock for Intel Atom^®-Based Systems
SMBus Table: Byte Count Register
Byte 8
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
BC4
BC3
BC2
BC1
BC0
Control Function
Byte Count Programming
Type
RW
RW
RW
RW
RW
0
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
PWD
0
0
0
0
1
1
1
1
SMBus Table: Watch Dog Timer Control Register
Byte 9
Bit 7
Bit 6
Bit 5
Name
HWD_EN
WD Hard Status
WDTCtrl
Control Function
Watchdog Hard Alarm Enable
WD Hard Alarm Status
Watch Dog Alarm Time base
Control
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HWD3
HWD2
HWD1
HWD0
Reserved
WD Hard Alarm Timer Bit 3
WD Hard Alarm Timer Bit 2
WD Hard Alarm Timer Bit 1
WD Hard Alarm Timer Bit 0
Reserved
Type
RW
R
0
Disable
Normal
1
Enable
Alarm
PWD
0
X
R
290ms Base
0
RW These bits represent X*290ms or X*1.16s. 1
RW The watchdog timer waits before it goes to 1
RW alarm mode. Default is 15 X 290ms =
1
RW
4.35s.
1
RW
-
-
0
SMBus Table: Skew programming Register
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
Control Function
CPUCLK0 Skew Control (ps)
CPUCLK1 Skew Control (ps)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See CPU Skew Programming Table
See CPU Skew Programming Table
PWD
0
0
0
0
0
0
0
0
CPU Skew Programming Table
Byte 10 bits [7:4]
or bits [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Skew Value (ps)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
IDT^® Low Power Clock for Intel Atom^®-Based Systems
1561A — 06/01/10
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