ICS9LPRS436CKILF Datasheet, PDF (12/20 Pages) Integrated Device Technology – Low Power Clock for Intel Atom®-Based Systems

ICS9LPRS436C
Low Power Clock for Intel Atom^®-Based Systems
General SMBus serial interface information for the ICS9LPRS436C
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 _(H)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 _(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 _(H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X_(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address D2_(H)
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
Byte N + X - 1
P
stoP bit
ACK
IDT^® Low Power Clock for Intel Atom^®-Based Systems
Index Block Read Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address D2_(H)
WR
WRite
Beginning Byte = N
RT
Repeat starT
ACK
ACK
Slave Address D3_(H)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N
Not acknowledge
P
stoP bit
12
Byte N + X - 1
1561A — 06/01/10