ICS9FG104 Datasheet, PDF (8/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG104
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0 Pin #
Name
Control Function Type 0
1
Bit 7
17
SEL14M_25M#¹
(FS3)
RW _{See Frequency}
Bit 6
6
Bit 5
24
Bit 4
25
Bit 3
16
FS2¹
FS1¹
FS0¹
Spread Enable¹
RW ^{Selection Table,}
RW
Page 1
RW
RW Off
On
PWD
Pin 17
Pin 6
Pin 24
Pin 25
Pin 16
Enable Software Control of Frequency,
Bit 2
-
Spread Enable (Spread Type always
Software Control)
Hardware Software
RW _{Select Select}
0
Bit 1
Bit 0
DIF_STOP# drive mode
SPREAD TYPE
RW Driven Hi-Z
0
RW Down Center 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1 Pin #
Name
Control Function
Bit 7
-
Reserved
Bit 6
-
DIF_3 EN
Output Enable
Bit 5
-
DIF_2 EN
Output Enable
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
DIF_1 EN
Output Enable
Bit 1
-
DIF_0 EN
Output Enable
Bit 0
-
Reserved
Type 0
RW Disable
RW Disable
RW Disable
RW Disable
1
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Stop Control Register
Byte 2 Pin #
Name
Control Function Type 0
1
PWD
Bit 7
-
Reserved
0
Bit 6
-
DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 5
-
DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 4
-
Reserved
0
Bit 3
-
Reserved
0
Bit 2
-
DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 1
-
DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 0
-
Reserved
0
0839D—06/02/05
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