ICS9FG104 Datasheet, PDF (14/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG104
N
INDEX
AREA
12
D
A2
e
b
c
E1 E
A
A1
-C-
SEATING
PLANE
aaa C
L
α
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
(25.6 mil)
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
--
1.20
--
.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.19
0.30
.007
.012
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
6.40 BASIC
0.252 BASIC
4.30
4.50
.169
.177
0.65 BASIC
0.0256 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
--
0.10
--
.004
VARIATIONS
N
28
D mm.
MIN
MAX
9.60
9.80
D (inch)
MIN
MAX
.378
.386
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9FG104yGLFT
Example:
ICS XXXX y G LF T
0839D—06/02/05
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
14