ICS9FG104 Datasheet, PDF (11/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG104
SMBus Table: PLL Frequency Control Register
Byte 10 Pin #
Name
Control Function
Bit 7
-
PLL N Div8 N Divider Prog bit 8
Bit 6
-
PLL N Div9 N Divider Prog bit 9
Bit 5
-
PLL M Div5
Bit 4
-
PLL M Div4
Bit 3
-
PLL M Div3
M Divider
Bit 2
-
PLL M Div2
Programming
Bit 1
-
PLL M Div1
bit (5:0)
Bit 0
-
PLL M Div0
Type 0
1
PWD
RW
The decimal
X
RW
representation of M and
N Divider in Byte 11 and
X
RW _{12 will configure the PLL} X
RW
VCO frequency.
X
RW ^{Default at power up =} X
RW ^{latch-in or Byte 0 Rom} X
RW
table. VCO Frequency
= 14.318 x
X
RW
[NDiv(9:0)+8] /
X
[MDiv(5:0)+2]
SMBus Table: PLL Frequency Control Register
Byte 11 Pin #
Name
Control Function
Bit 7
-
PLL N Div7
Bit 6
-
PLL N Div6
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
N Divider
Programming Byte11
bit(7:0) and Byte10
bit(7:6)
Bit 0
-
PLL N Div0
Type 0
1
PWD
RW
The decimal
X
RW ^{representation of M and} X
RW
N Divider in Byte 11 and
12 will configure the PLL
X
RW
VCO frequency.
X
RW Default at power up = X
RW ^{latch-in or Byte 0 Rom} X
RW ^{table. VCO Frequency} X
= 14.318 x
RW
[NDiv(9:0)+8] /
X
[MDiv(5:0)+2]
SMBus Table: PLL Spread Spectrum Control Register
Byte 12 Pin #
Name
Control Function
Bit 7
-
PLL SSP7
Bit 6
-
PLL SSP6
Bit 5
-
PLL SSP5
Bit 4
-
PLL SSP4
Spread Spectrum
Bit 3
-
PLL SSP3 Programming bit(7:0)
Bit 2
-
PLL SSP2
Bit 1
-
PLL SSP1
Bit 0
-
PLL SSP0
Type 0
1
RW
RW
RW
These Spread
RW
Spectrum bits in Byte
13 and 14 will program
RW _{the spread pecentage}
RW
of PLL
RW
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 13 Pin #
Name
Control Function Type 0
1
Bit 7
-
Reserved
Bit 6
-
PLL SSP14
RW
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP9
RW
These Spread
Spread Spectrum
Programming bit(14:8)
RW
RW
RW
Spectrum bits in Byte
13 and 14 will program
the spread pecentage
of PLL
RW
Bit 0
-
PLL SSP8
RW
PWD
0
X
X
X
X
X
X
X
0839D—06/02/05
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