ICS9FG104 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
Pin Description
PIN #
PIN NAME
1 XIN/CLKIN
2 X2
3 VDD
4 GND
5 REFOUT
6 FS2
7 DIF_3
8 DIF_3#
9 VDD
10 GND
11 DIF_2
12 DIF_2#
13 SDATA
14 SCLK
15 DIF_STOP#
16 SPREAD
17 SEL14M_25M#
18 DIF_1#
19 DIF_1
20 GND
21 VDD
22 DIF_0#
23 DIF_0
24 FS1
25 FS0
26 IREF
27 GNDA
28 VDDA
ICS9FG104
PIN TYPE
DESCRIPTION
IN
OUT
PWR
IN
IN
IN
IN
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
PWR
PWR
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin.
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock outputs
0.7V differential complement clock outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up resistor,
to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 =
25 MHz
0.7V differential complement clock outputs
0.7V differential true clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Frequency select pin.
Frequency select pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
0839D—06/02/05
2