ICS9FG104 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG104
SMBus Table: Byte Count Register
Byte 6 Pin #
Name
Control Function Type 0
Bit 7
-
BC7
RW
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
BC6
Writing to this register ^RW
-
BC5
will configure how ^RW
-
BC4
many bytes will be ^RW
-
BC3
read back, default is ^RW
-
BC2
07 = 7 bytes.
RW
-
BC1
RW
-
Bit 0
-
BC0
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
1
-
1
-
1
SMBus Table: Reserved Register
Byte 7 Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control Function Type 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: Reserved Register
Byte 8 Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control Function Type 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: M/N Programming Enable
Byte 9 Pin #
Name
Control Function
Bit 7
-
M/N_Enable
M/N Prog. Enable
Bit 6
-
Reserved
Bit 5
5
REFOUT_En
REFOUT Enable
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
Reserved
Bit 1
-
Reserved
Bit 0
-
Reserved
Type 0
RW Disable
RW Disable
1
Enable
Enable
PWD
0
1
1
0
0
0
0
0
0839D—06/02/05
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