ICS9FG104 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG104
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Storage Temperature
Tambient
Ambient Operating Temp
Tcase
Case Temperature
Input ESD protection
ESD prot
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up _-5
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
V_DD + 0.3 V
1
0.8
V
1
5
uA
1
uA
1
uA
1
Operating Supply Current
I_DD3.3OP
Full Active, C_L = Full load;
f = 400 MHz
Full Active, C_L = Full load;
f = 100 MHz
125 150 mA
1
110 125 mA
1
I_DD3.3STOP
All outputs stopped driven
All outputs stopped Hi-Z
106 120 mA
1
48 60 mA
1
Input Frequency³
F_i
V_DD = 3.3 V
14
25 MHz 3
Pin Inductance¹
L_pin
7
nH
1
Input/Output
Capacitance¹
C_IN
C_OUT
Logic Inputs
1.5
Output pin capacitance
5
pF
1
6
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up and after
input clock stabilization to 1st
1.8 ms 1,2
clock
Modulation Frequency
f_MOD
Triangular Modulation
30
33 kHz
1
DIF output enable
t_DIFOE
DIF output enable after
DIF_Stop# de-assertion
15
ns
1
Input Rise and Fall times
t_R/t_F
20% to 80% of VDD
5
ns
1
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to}
meet
0839D—06/02/05
4