ICS9248-199 Datasheet, PDF (8/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
Byte 16: Output Divider Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
AGP 50MHz Div 3
AGP 50MHz Div 2
AGP 50MHz Div 1
AGP 50MHz Div 0
PWD
X
X
X
X
X
X
X
X
Description
PCI clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to Table 2. Default at
power up is latched FS divider.
AGP clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to Table 1. Default at
power up is latched FS divider.
Byte 17: Output Divider Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
SD_INV
CPU_INV
AGP 66MHz Div 3
AGP 66MHz Div 2
AGP 66MHz Div 1
AGP 66MHz Div 0
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
SDRAM Phase Inversion bit
CPUCLK Phase Inversion bit
AGP clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to table 1. Default at
power up is latched FS divider.
Table 1
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/2 /4 /8 /16
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Div (3:2)
00 01 10 11
Div (1:0)
00
/4 /8 /16 /32
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
* These bytes are not available in ICS9248A/B/CF-199.
Programmable features on these bytes are only for ICS9248D/EF-199.
0376E—12/23/02
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