ICS9248-199 Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS9248-199. The minimum that the CPU clock is enabled
(CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled.
The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width
is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS9248-199.
3. All other clocks continue to run undisturbed.
0376E—12/23/02
17