ICS9248-199 Datasheet, PDF (6/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
Byte 8: Byte Count Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0 _{Note: Writing to this register will configure}
0 _{byte count and how many bytes will be}
1 ^{read back, default is 0F}H ^{= 15 bytes.}
1
1
1
Byte 9: Watchdog Timer Count Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits
correspond to X • 290ms the watchdog
1 _{timer will wait before it goes to alarm mode}
0 ^{and reset the frequency to the safe setting.}
0
0
Default at power up is 16 • 290ms = 4.6
seconds.
0
Byte 10: Programming Enable bit 8 Watchdog Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Program
Enable
WD Enable
WD Alarm
SF4
SF3
SF2
SF1
SF0
PWD
Description
Programming Enable bit
0
0 = no programming. Frequencies are selected by
HW latches or Byte0
1 = enable all I²C programing.
0 Watchdog Enable bit
0 Watchdog Alarm Status 0 = normal 1= alarm status
0
1 Watchdog safe frequency bits. Writing to these bits
0 will configure the safe frequency corrsponding to
0 Byte 0 Bit 2, 7:4 table
0
Byte 11: VCO Frequency M Divider (Reference divider) Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
Description
X N divider bit 8
X
X
X ^{The decimal respresentation of Mdiv (6:0)}
X
corresposd to the reference divider value.
Default at power up is equal to the latched
X _{inputs selection.}
X
X
* These bytes are not available in ICS9248A/B/CF-199.
Programmable features on these bytes are only for ICS9248D/EF-199.
0376E—12/23/02
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