ICS9248-199 Datasheet, PDF (7/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
Byte 12: VCO Frequency N Divider (VCO divider) Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X _{The decimal representation of Ndiv (8:0)}
X _{correspond to the VCO divider value.}
X _{Default at power up is equal to the latched}
X ^{inputs selecton. Notice Ndiv 8 is located in}
X ^{Byte 11.}
X
X
Byte 13: Spread Spectrum Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
X
The Spread Spectrum (12:0) bit will
program the spread precentage. Spread
precent needs to be calculated based on
X _{the VCO frequency, spreading profile,}
X ^{spreading amount and spread frequency. It}
X ^{is recommended to use ICS software for}
X
spread programming. Default power on is
latched FS divider.
X
Byte 14: Spread Spectrum Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
Description
X Reserved
X Reserved
X Reserved
X Spread Spectrum Bit 12
X Spread Spectrum Bit 11
X Spread Spectrum Bit 10
X Spread Spectrum Bit 9
X Spread Spectrum Bit 8
Byte 15: Output Divider Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SD Div 3
SD Div 2
SD Div 1
SD Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
X
X
X
X
X
X
X
X
Description
SDRAM clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
CPU clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
* These bytes are not available in ICS9248A/B/CF-199.
Programmable features on these bytes are only for ICS9248D/EF-199.
0376E—12/23/02
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