ICS9248-199 Datasheet, PDF (10/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
Byte 21: Slew Rate Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
24/48_Slew 1
24/48_Slew 0
AGP_Slew 1
AGP_Slew 0
APIC_Slew 1
APIC_Slew 0
REF_Slew 1
REF_Slew 0
PWD
Description
0 _{24/48 MHz clock slew rate control bits.}
1 ^{01 = strong; 00, 11 = normal; 10 = weak}
0 _{AGP clock slew rate control bits.}
1 ^{10 = strong; 00, 11 = normal; 01 = weak}
0 _{IOAPIC clock slew rate control bits.}
1 ^{00 = strong; 00, 11 = normal; 10 = weak}
0 _{REF clock slew rate control bits.}
1 ^{10 = strong; 00, 11 = normal; 00 = weak}
Byte 22: Slew Rate Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
PCICLK_F 1x2x
PCICLK0
Reserved
Reserved
Reserved
Reserved
PWD
0 Reserved
0 Reserved
0 0:1x, 1:2x
0 0:1x, 1:2x
0 Reserved
0 Reserved
0 Reserved
0 Reserved
Description
Byte 23: Slew Rate Control Register*
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
48MHz Slew 1
CPUCLKT/C
Slew 1
CPUCLK Slew 1
SD Slew 1
PWD
Description
0 _{48MHz clock slew rate control bits.}
1 ^{01 = strong; 00, 11 = normal;10 = weak}
0 _{CPUCLKT/C0 clock slew rate control bit.}
1 ^{01 = strong; 00, 11 = normal;10 = weak}
0 _{CPUCLK clock slew rate control bits.}
1 ^{01 = strong; 00, 11 = normal;10 = weak}
0 _{SDRAM clock slew rate control bits.}
1 ^{01 = strong; 00, 11 = normal;10 = weak}
Bit 24: Control, Active/Inactive Register*
(1 = enable, 0 = disable)
Bit
Bit 7
PIN#
-
PWD
0
DESCRIPTION
Res erv ed
Bit 6
-
0
Res erv ed
Bit 5
-
0
Res erv ed
Bit 4
-
0
Res erv ed
Bit 3
9
0
PCICLK_F (Act/Inactive)
Bit 2
44
0
CPUCLKT0 (Act/Inactive)
Bit 1
43
0
CPUCLK_C0 (Act/Inactive)
Bit 0
40
1
CPUCLK (Act/Inactive)
* These bytes are not available in ICS9248A/B/CF-199.
Programmable features on these bytes are only for ICS9248D/EF-199.
0376E—12/23/02
10