ICS9248-199 Datasheet, PDF (2/21 Pages) Integrated Circuit Systems – Frequency Generator for SIS 735/740 with AMD K7 Processor

ICS9248-199
Pin Configuration
PIN NUMBER
1, 11, 17, 21, 25,
36
2
3
4, 5, 8, 14, 20,
24, 26, 34, 39,
42, 46
6
7
9
10
12
16, 15, 13
19, 18
22
23
27
28
29
PIN NAME
VDD
FS0
REF0
FS1
REF1
GND
X1
X2
FS2
PCICLK_F
FS3
PCICLK0
FS4
PCICLK1
PCICLK (4:2)
AGPCLK (1:0)
48MHz
AGPSEL
24_48MHz
SCLK
SDATA
AGP_STOP#
30
SDRAM_STOP#
31
32
33
35
37, 38
40
41, 45, 48
43
PD#
CPU_STOP#
PCI_STOP#
SDRAM
NC
CPUCLK
VDDL
CPUCLKC0
44
47
0376E—12/23/02
CPUCLKT0
IOAPIC
TYPE
PWR
IN
OUT
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
I/O
IN
IN
IN
IN
IN
OUT
-
OUT
PWR
OUT
OUT
OUT
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
48MHz output clock.
AGP frequency select pin.
Clock output for super I/O/USB default is 24MHz.
Clock pin of I²C circuitry 5V tolerant.
Data pin for I²C circuitry 5V tolerant.
Stops all AGP clocks besides the AGP_F clocks at logic 0 level,
when input low.
Stops all SDRAM clocks at logic 0 level, when input low
(when MODE active).
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
Stops all CPUCLKs clocks at logic 0 level, when input low.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low.
SDRAM clock output.
No connect pins.
CPU clock output.
Supply for CPU and IOAPIC clocks at 2.5V nominal.
Complementary clocks of differential pair CPU outputs. This clock is
180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. This clock is in phase
with SDRAM clocks. This open drain output needs an external 1.5V
pull-up.
2.5V clock output.
2