ICS950813 Datasheet, PDF (7/22 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950813
Advance Information
BYTE
3
Pin #
Affected Pin
Name
Control Function
Bit 7
38
48MHz_DOT
Output control
Bit 6
39
48MHz_USB/FS2**
Output control
Bit 5
7 *ASEL/PCICLK_F2 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 4
6
PCICLK_F1 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 3
5
PCICLK_F0 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 2
7
*ASEL/PCICLK_F2
Output control
Bit 1
6
PCICLK_F1
Output control
Bit 0
5
PCICLK_F0
Output control
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
BYTE
4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
35
33
33
35
24
23
22
21
Affected Pin
Name
FS3
FS4
3V66_0/FS4**
3V66_1/VCH_CLK/FS3**
3V66_5
3V66_4
3V66_3
3V66_2
Control Function
Frequency Selection
Frequency Selection
Output control
Output control
Output control
Output control
Output control
Output control
Type
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
Disable
Disable
Freerun
Freerun
Freerun
Disable
Disable
Disable
1
Enable
Enable
Not
Freerun
Not
Freerun
Not
Freerun
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
-
-
-
-
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
PWD
X
X
1
1
1
1
1
1
BYTE
5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
38
39
Affected Pin
Name
PD Mode Iref Mirror Enable
Reserved
3V66(5:2) (See table 6)
3V66(1:0) (See table 7)
48MHz_DOT Slew Control
48MHz_USB Slew Control
Control Function
Allow Iref Mirror to be ON during
Power Down Mode
Reserved
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
00 = Medium (default), 01 = Low,
11,10 =High
00 = Medium (default), 01 = Low,
11,10 =High
Note: Functions in Byte 5 of CK408 were intended as a test and debug byte only.
Type
Bit Control
0
1
RW OFF
ON
X
-
-
X
Freerun
Not
Freerun
X
Freerun
Not
Freerun
RW
-
-
RW
-
-
RW
-
-
RW
-
-
PWD
0
0
0
0
0
0
0
0
BYTE
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Control Function
Revision ID Value Based on
Device Revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Type
R
R
R
R
R
R
R
R
Bit Control
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
0708—10/10/02
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