ICS950813 Datasheet, PDF (2/22 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950813
Advance Information
Pin Description
PIN # PIN NAME
1 VDDREF
2 X1
3 X2
4 GND
5 PCICLK_F0
6 PCICLK_F1
7 *ASEL/PCICLK_F2
8 VDDPCI
9 GND
10 PCICLK0
11 **E_PCICLK1/PCICLK1
12 PCICLK2
13 **E_PCICLK3/PCICLK3
14 VDDPCI
15 GND
16 PCICLK4
17 PCICLK5
18 PCICLK6
19 VDD3V66
20 GND
21 3V66_2
22 3V66_3
23 3V66_4
24 3V66_5
25 *PD#
26 VDDA
27 GND
28 Vtt_PWRGD#
PIN TYPE
PWR
IN
OUT
PWR
OUT
OUT
I/O
PWR
PWR
OUT
I/O
OUT
I/O
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Asynchronous AGP/PCI frequency latch input pin / 3.3V PCI free running
clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
Early/Normal PCI clock output latched at power up.
PCI clock output.
Early/Normal PCI clock output latched at power up.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Asynchronous active low input pin used to power down the device into a low
IN
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 3ms.
PWR
PWR
IN
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
0708—10/10/02
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