ICS950813 Datasheet, PDF (3/22 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950813
Advance Information
Pin Description (Continued)
PIN # PIN NAME
29 SDATA
30 SCLK
31 GND
32 VDD3V66
33 3V66_0/FS4**
34 PCI_STOP#*
35 3V66_1/VCH_CLK/FS3**
36 GND
37 VDD48
38 48MHz_DOT
39 48MHz_USB/FS2**
40 PWRSAVE#*
41 GND
42 IREF
43 MULTSEL*
44 CPUCLKC2
45 CPUCLKT2
46 VDDCPU
47 GND
48 CPUCLKC1
49 CPUCLKT1
50 VDDCPU
51 CPUCLKC0
52 CPUCLKT0
53 CPU_STOP#*
54 FS0
55 FS1
56 REF
PIN TYPE
I/O
IN
PWR
PWR
I/O
IN
I/O
PWR
PWR
OUT
I/O
IN
PWR
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
PWR
OUT
OUT
IN
IN
IN
OUT
DESCRIPTION
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
Power pin for the 3V66 clocks.
Frequency select latch input pin / 3.3V 66.66MHz clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz
VCH clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
48MHz clock output.
Frequency select latch input pin / 3.3V 48MHz clock output.
Real Time input pin to change frequency to under-clock entries located in
FS 4:2 = '100'. Clock groups gear ratio will not be change during this
operation.
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selection the current multiplier for CPU outputs
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Stops all CPUCLK besides the free running clocks
Frequency select pin.
Frequency select pin.
14.318 MHz reference clock.
Power Supply
Pin Number
VDD
GND
1
4
37
36
46
47
Description
Xtal, Ref, CPU PLL, digital
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
0708—10/10/02
3