ICS950813 Datasheet, PDF (16/22 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950813
Advance Information
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1)
Tpci
Tepci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
SYMBOL
CONDITIONS
3V66 to PCI^1,2
S_3V66-PCI 3V66 (5:0) leads 33MHz PCI
1_{Guarenteed by design, not 100% tested in production.}
MIN TYP MAX
1.5 2.55 3.5
2_{500ps Tolerance}
UNITS
ns
E_PCICLK to PCICLK Skews
GROUP
SYMBOL
CONDITIONS
T_{E_PCI-PCI1}
E_PCICLK1 (pin 11)=0
E_PCICLK3 (pin 13)=1
E_PCICLK to PCICLK¹
T_{E_PCI-PCI2}
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=0
T_{E_PCI-PCI3}
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=1
1_{Guaranteed by design, not 100% tested in production.}
MIN TYP MAX UNITS
0.3 0.5 0.7
ns
0.8 1.0 1.2
ns
1.3 1.5 1.7
ns
0708—10/10/02
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