ICS950813 Datasheet, PDF (1/22 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

Integrated
Circuit
Systems, Inc.
ICS950813
Advance Information
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
Pin Configuration
processor.
VDDREF 1
56 REF
X1 2
55 FS1
Output Features:
X2 3
54 FS0
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
GND 4
PCICLK_F0 5
PCICLK_F1 ₆
53 CPU_STOP#*
52 CPUCLKT0
51 ^CPUCLKC0
• 3 PCI_F (3.3V) @ 33.3MHz
*ASEL/PCICLK_F2 7
50 VDDCPU
• 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
VDDPCI 8
GND 9
PCICLK0 10
49 CPUCLKT1
48 CPUCLKC1
47 GND
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
**E_PCICLK1/PCICLK1 11
PCICLK2 12
**E_PCICLK3/PCICLK3 13
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
Features:
VDDPCI 14
43 MULTSEL*
• Provides standard frequencies and additional 3%, 5%
and 10% over-clocked frequencies
• Supports spread spectrum modulation:
No spread, Center Spread (±0.3%, ±0.55%), or Down
Spread (-0.5%, -0.75%)
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
42 IREF
41 GND
40 PWRSAVE#*
39 48MHz_USB/FS2^**
38 48MHz_DOT
37 VDD48
• Offers adjustable PCI early clock via latch inputs
• Selectable 1X or 2X strength for REF via I²C interface
• Programmable group to group skew
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
36 GND
35 3V66_1/VCH_CLK/FS3^**
34 PCI_STOP#*
33 3V66_0/FS4^**
• Linear programmable frequency and spreading %
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
32 VDD3V66
31 GND
30 SCLK
29 SDATA
• Uses external 14.318MHz crystal
• Stop clocks and functional control available through
I²C interface.
56-Pin 300mil SSOP
56-Pin 240mil TSSOP
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
*_{These inputs have 120K internal pull-up resistors to VDD.}
**_{Internal pull-down resistors to ground.}
Block Diagram
Functionality Table
PLL2
X1
XTAL
X2
OSC
PWRSAVE#
Vtt_PWRGD#
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (4:0)
SDATA
SCLK
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
48MHz_USB
48MHz_DOT
3V66 (5:2)
REF
3 ^{CPUCLKT (2:0)}
3 ^{CPUCLKC (2:0)}
PCICLK (6:0)
7
PCICLK_F (2:0)
3
3V66_0
3V66_1/VCH_CLK
I REF
FS1 FS0
CPU
MHz
0
0 100.00
0
1 133.33
1
0
200.00
1
1
166.66
AGP
MHz
66.67
66.67
66.67
66.66
PCI
MHz
33.33
33.33
33.33
33.33
Asynchronous AGP/PCI Frequency Selection Table
Byte7 Bit5 Byte7 Bit4 AGP Frequency PCI Frequency
0
0
66.00
33.00
0
1
75.43
37.72
1
0
1
1
88.00
--
44.00
--
0708—10/10/02
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.