ICS9250-38 Datasheet, PDF (7/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High
Voltage
Input Low
Voltage
Input High
Current
Input Low
Current
Operating Supply
Current
Powerdown
Current
Input Frequency
Pin Inductance
Input
Capacitance¹
Transition time¹
Settling time¹
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
I_DD3.3OP
I_DD3.3OP
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_trans
T_s
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = Full load; Select @ 100 MHz
C_L =Full load; Select @ 133 MHz
C_L = Full load; Select @ 200 MHz
IREF=2.32 mA
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
2
V_DD + 0.3 V
V_SS - 0.3
0.8
V
-5
5
-5
-200
229 240
360
220 236
360
234 245
360
25
14.32
7
5
6
27
36
45
3
3
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ms
Clk Stabilization^{1 T}STAB ^{From V}DD ^{= 3.3 V to 1% target frequency}
Delay¹
t_PZH,t_PZL Output enable delay (all outputs)
t_PHZ,t_PLZ Output disable delay (all outputs)
1
1
1_{Guaranteed by design, not 100% tested in production.}
3
ms
10
ns
10
ns
0404B—12/23/02
7