ICS9250-38 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Pin#
X
X
X
X
X
Name
48MHz_USB
48MHz_USB
48MHz_DOT
48MHz_DOT
66MHz_OUT[2:0]
Bit 5
X
Bit 6
X
Bit 7
X
66MHz_OUT[2:0]
-
-
PWD²
0
0
0
0
0
0
0
0
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
X
X
X
X
X
X
X
X
Name
Vendor ID Bit0
Vendor ID Bit1
Vendor ID Bit2
Vendor ID Bit3
Revision ID Bit0
Revision ID Bit1
Revision ID Bit2
Revision ID Bit3
PWD²
1
0
0
0
X
X
X
X
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
Type¹
RW
RW
RW
RW
RW
RW
-
-
Description
USB edge rate cntrol
USB edge rate cntrol
DOT edge rate control
DOT edge rate control
T_pd 66MHz_IN to 66MHz_OUT
propagation delay control
T 66MHz_IN to 66MHz_OUT
pd
propagation delay control
(Reserved)
(Reserved)
Type¹
R
R
R
R
R
R
R
R
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Description
Revision ID values will be based on
individual device's revision
0404B—12/23/02
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