ICS9250-38 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Pin Configuration
PIN NUMBER
1, 8, 14, 19, 26,
32, 37, 46, 50
2
PIN NAME
VDD
X1
3
X2
7, 6, 5
4, 9, 15, 20, 27,
31, 36, 41, 47
18, 17, 16, 13,
12,11, 10
23, 22, 21
24
25
PCICLK_F (2:0)
GND
PCICLK (6:0)
66MHz_OUT (2:0)
3V66 (4:2)
66MHz_IN
3V66_5
PD#
28
Vtt_PWRGD#
29
SDATA
30
SCLK
33
3V66_0
34
PCI_STOP#
35
38
39
40
42
43
44, 48, 51
45, 49, 52
3V66_1/VCH_CLK
48MHz_DOT
48MHz_USB
FS2
I REF
MULTSEL0
CPUCLKC (2:0)
CPUCLKT (2:0)
53
55, 54
56
CPU_STOP#
FS (1:0)
REF
TYPE
DESCRIPTION
PWR
3.3V power supply
X2 Crystal Input
X1 Crystal
Output
OUT
Crystal input,nominally 14.318MHz, with internal loading cap.
Crystal output, nominally 14.318MHz, with internal loading cap.
Free running PCI clock not affected by PCI_STOP# for power
management as a function of the I²C stop control bits.
PWR
Ground pins for 3.3V supply
OUT
OUT
OUT
IN
OUT
IN
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
PCI clock outputs
66MHz buffered 66MHz_OUT from 66MHz_IN input.
66MHz reference clocks, from internal VCO
66MHz input to buffered 66MHz_OUT and PCI clocks
66MHz reference clock, from internal VCO
Invokes power-down mode. Active Low.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS[0:2] and MULTISEL0 inputs are valid and are ready to be
sampled
(active low)
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
66MHz reference clocks, from internal VCO
Stops all PCICLKs at logic 0 level, when input low besides the PCICLK_F
clocks which are controllable by I2C bits whether they are free running or
stopped by PCI_STOP.
3.3V output selectable through I²C to be 66MHz from internal VCO or
48MHz (non-SSC)
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
Stops all CPUCLKs at logic 0 level, when input low. The individual CPU clocks
are controllable by I2C bits whether they are free running or stopped by
CPU_STOP.
Frequency select pins
14.318MHz reference clock.
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
0404B—12/23/02
2