ICS9250-38 Datasheet, PDF (4/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Byte 0: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
54
55
40
Name
FS0
FS1
FS2
Bit 3
34
PCI_STOP#³
Bit 4
Bit 5
Bit 6
Bit 7
53
CPU_STOP#
35
3V66_1/VCH
-
- Spread Enabled
PWD²
X
X
X
X
1
X
0
0
0
Type¹
R
R
R
R
RW
R
RW
RW
Description
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Reflects the value of FS2 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
pin sampled on PWD
Software mode:
0=PCICLK stopped
1=PCICLK not stopped
Reflects the current value of the external
CPU_STOP# pin
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
(Reserved)
0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
52, 51
49, 48
45, 44
52, 51
49, 48
45, 44
-
43
Name
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
-
MULTSEL0
PWD²
1
1
1
0
0
0
0
X
Type¹
RW
RW
RW
RW
RW
RW
-
R
Description
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
Allow control of CPUCLKT0/C0 with assertion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT1/C1 with assertion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT2/C2 with assertion of
CPU_STOP# 0=Not free running 1=Free running
(Reserved)
Reflects the current value of MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I²C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I²C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I²C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I²C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
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