ICS9250-38 Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

Integrated
Circuit
Systems, Inc.
ICS9250-38
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK 408 clock for Almador-M mobile chipset with Tualatin
PIII processor.
Pin Configuration
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 1 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
• 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
• 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
• Almador Chipset has a DLL driving the clock buffer
path for the 3 buffer path 66.6 MHz outputs,
66Buf(0:2).
Almador board level designs MUST use pin 22,
66Buf_1, as the feedback connection from the
clock buffer path to the Almador (GMCH)
chipset.
VDDREF
1
X1
2
X2
3
GND
4
PCICLK_F0
5
PCICLK_F1
6
PCICLK_F2
7
VDDPCI
8
GND
9
PCICLK0
10
PCICLK1
11
PCICLK2
12
PCICLK3
13
VDDPCI
14
GND
15
PCICLK4
16
PCICLK5
17
PCICLK6
18
VDD3V66
19
GND
20
66MHz_OUT0/3V66_2
21
66MHz_OUT1/3V66_3
22
66MHz_OUT2/3V66_4
23
66MHz_IN/3V66_5
24
*PD#
25
VDDA
26
GND
27
Vtt_PWRGD#
28
56
REF
55
FS1
54
FS0
53
CPU_STOP#*
52
CPUCLKT0
51
CPUCLKC0
50
VDDCPU
49
CPUCLKT1
48
CPUCLKC1
47
GND
46
VDDCPU
45
CPUCLKT2
44
CPUCLKC2
43
MULTSEL0*
42
I REF
41
GND
40
FS2
39
48MHz_USB
38
48MHz_DOT
37
VDD48
36
GND
35
3V66_1/VCH_CLK
34
PCI_STOP#*
33
3V66_0
32
VDD3V66
31
GND
30
SCLK
29
SDATA
56-Pin 300mil SSOP/TSSOP
• Supports spread spectrum modulation,
* These inputs have 150K internal pull-up resistor to VDD.
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• 66MHz Output Jitter (Buffered Mode Only) <100ps
• CPU Output Skew <100ps
Functionality
Block Diagram
PLL2
X1
XTAL
X2
OSC
48MHz_USB
48MHz_DOT
3V66_1/VCH_CLK
FS2
FS1
FS0
CPU
(MHz)
3V66
(MHz)
66Buff[2:0]
3V66[4:2]
(MHz)
0
0
0 66.66 66.66
66.66
0
0
1 100.00 66.66
66.66
0
1
0 200.00 66.66
66.66
PCI_F
PCI
(MHz)
33.33
33.33
33.33
66MHz_IN
REF
0
1
1 133.33 66.66
66.66
33.33
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
3 ^{CPUCLKT (2:0)}
3 ^{CPUCLKC (2:0)}
1
0
0 66.66 66.66 66MHz_IN 66MHz_IN/2
1
0
1 100.00 66.66 66MHz_IN 66MHz_IN/2
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
66MHz
DIVDER
3V66
DIVDER
PCICLK (6:0)
7
PCICLK_F (2:0)
3
66MHz_OUT (2:0)
3
3V66 (5:2,0)
5
I REF
1
1
1
1
Mid 0
Mid 0
Mid 1
Mid 1
0 200.00 66.66 66MHz_IN 66MHz_IN/2
1 133.33 66.66 66MHz_IN 66MHz_IN/2
0 Tristate Tristate Tristate
Tristate
1 TCLK/2 TCLK/4 TCLK/4
TCLK/8
0 Reserved Reserved Reserved Reserved
1 Reserved Reserved Reserved Reserved
0404B—12/23/02