ICS9250-38 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD²
1
1
1
1
1
1
1
0
Type¹
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
5
6
7
5
6
7
39
38
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F0
PCICLK_F1
PCICLK_F2
48MHz_USB
48MHz_DOT
PWD²
1
1
1
0
0
0
1
1
Type¹
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
PWD²
1
1
1
1
1
1
0
0
Type¹
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
0=Disabled 1=Enabled ⁴
(Reserved)
(Reserved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
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