ICS9250-38 Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS9250-38
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There
is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1
is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks.
The PCI group should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max
propagation value.
66MHz_IN
Tpd
66MHz_OUT
PCICLK_F
3V66
Tpci
No Relationship
Group Skews at Common Transition Edges: (Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
3V66
3V66 3V66 (1:0) pin to pin skew
0
66MHz_OUT
66OUT 66MHz_OUT (2:0) pin to pin skew
0
PCI
PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0
66MHz_IN
66MHz_OUT
Tpd ^{Propogation delay from 66MHz_IN to}
2.5
66MHz_OUT (2:0)
66MHz_OUT to PCI Tpci 66MHz_OUT (2:0) leads 33 MHz PCI
1.5
1_{Guaranteed by design, not 100% tested in production.}
TYP
MAX UNITS
500 ps
175 ps
500 ps
4.5 nS
3.5 nS
0404B—12/23/02
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