ICS9250-28 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Maximum Case Operating Temperature . . . . . . +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
V_IL
I_IH
V_IN = V_DD
I_IL1 V_IN = 0 V; Inputs with no pull-up resistors
I_IL2 V_IN = 0 V; Inputs with pull-up resistors
2
V_SS-0.3
-5
-5
-200
V_DD+0.3
0.8
5
I_DD3.3OP
C_L = 0 pF; @ 66/100 MHz
C_L = 0 pF; @ 100/100 MHz
C_L = 0 pF; @ 133/133 MHz
C_L = 0 pF; @ 133/100 MHz
C_L = Max loads; @ 66/100 MHz
C_L = Max loads; @ 100/100 MHz
C_L = Max loads; @ 133/133 MHz
138 200
126 200
172 200
141 200
339 400
328 400
383 450
Operating Supply
C_L = Max loads; @ 133/100 MHz
340 400
Current
C_L = 0 pF; @ 66/100 MHz
9
15
I_DD2.5OP
C_L = 0 pF; @ 100/100 MHz
C_L = 0 pF; @ 133/133 MHz
C_L = 0 pF; @ 133/100 MHz
C_L = Max loads; @ 66/100 MHz
C_L = Max loads; @ 100/100 MHz
11
18
13
20
13
20
13
35
23
60
C_L = Max loads; @ 133/133 MHz
29
60
Powerdown Current
Input Frequency
Transition time¹
Settling time¹
Clk Stabilization¹
Delay¹
I_DD3.3PD
I_DD.25PD
F_i
T_trans
T_s
T_STAB
t_PZH,t_PZL
t_PHZ,t_PLZ
C_L = Max loads; @ 133/100 MHz
C_L = Max loads
Input address VDD or GND
V_DD = 3.3 V
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V_DD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
30
60
251 400
<1
10
12 14.318 16
3
3
3
1
10
1
10
1_{Guaranteed by design, not 100% tested in production.}
UNITS
V
V
µA
µA
mA
mA
mA
mA
µA
MHz
ms
ms
ms
ns
ns
7