ICS9250-28 Datasheet, PDF (16/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-28
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in
all places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
Ferrite
Bead
C2
22µF/20V
Tantalum
1
2
3
4
5
2
C1
6
C1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C2
22µF/20V
Ferrite
Bead
Tantalum
VDD
56
55
54
53
C3
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2.5V Power Route
1
Clock Load
Ground
3.3V Power Route
16