ICS9250-28 Datasheet, PDF (5/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Name
- Reserved ID
- Reserved ID
- Reserved ID
- Reserved ID
-
SpreadSpectrum
(1=On/0=Off)
27 48MHz 1
26 48MHz 0
- Reserved ID
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
0 (Active/Inactive)
Note: Reserved ID bits must be written as "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 38 SDRAM7
Bit 6 41 SDRAM6
Bit 5 42 SDRAM5
Bit 4 45 SDRAM4
Bit 3 46 SDRAM3
Bit 2 47 SDRAM2
Bit 1 50 SDRAM1
Bit 0 51 SDRAM0
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 12 3V66-2 (AGP)
Bit 6 29 SDRAM12
Bit 5 32 SDRAM11
Bit 4 33 SDRAM10
Bit 3 36 SDRAM9
Bit 2 37 SDRAM8
Bit 1 16 PCICLK1
Bit 0 - Reserved
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
0 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
5