ICS9250-28 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-28
Truth Table
FS2 FS0 FS1
CPU
0 0X
0 1X
Tristate
TCLK/2
1 0 0 66.6 MHz
1 1 0 100 MHz
1 0 1 133 MHz
1 1 1 133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
PCI
Tristate Tristate
TCLK/3 TCLK/6
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
IOAPIC
Tristate
Tristate
TCLK
TCLK/6
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit 0
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
Undefined bit (Note 3)
Bit 0 FS0
FS1
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
Desctiption
CPUCLK SDRAM
MHz MHz
66.66 100.0
100.0 100.0
133.32 133.32
133.32 100.0
66.66 100.0
100.0 100.0
133.32 133.32
133.32 133.32
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
PCICLK IOAPIC
MHz MHz
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
PWD
0
0
0
0
0
X
X
0
Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
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