ICS9250-28 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-28
General Description
The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
1
IOAPIC
2, 56
VDDL
FS1
4
REF0
5, 9, 14, 20, 25,
31, 35, 40, 44, 49
VDD
6
X1
7
X2
3, 8, 13, 17, 19,
24, 30, 34, 39, GND
43, 48, 52, 55
12, 11, 10 3V66 (2:0)
28, 18
FS (2, 0)
16, 15
PCICLK[1:0]
21
PD#
22
SCLK
TYPE
DESCRIPTION
OUT 2.5V clock output running at 33.3MHz.
PWR 2.5V power supply for CPU & IOAPIC
IN Function Select pin. Determines CPU frequency, all output functionality
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
IN
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
OUT 3.3V PCI clock outputs
Asynchronous active low input pin used to power down the device into
IN
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
IN Clock pin of I²C circuitry 5V tolerant
23
SDATA
I/O Data pin for I²C circuitry 5V tolerant
26, 27
48MHz_0
29, 32, 33, 36,
37, 38, 41, 42,
45, 46, 47, 50, 51
SDRAM
(12:0)
54, 53
CPUCLK (1:0)
OUT 3.3V Fixed 48MHz clock outputs.
OUT
OUT
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I²C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (2:0) pins.
2