ICSSSTUB32872A Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – 28-Bit Registered Buffer for DDR2

Parity Functionality Block Diagram
21
21
Dn
DQ
D
PARIN
D
CLOCK
ICSSSTUB32872A
Advance Information
Qn
D
LATCHING AND
RESET FUNCTION
see Note (1)
PTYERR
(1) This function holds the error for two
cycles. See functional description and
timing diagram.
002aaa417
1222F—3/13/07
6