ICSSSTUB32872A Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – 28-Bit Registered Buffer for DDR2

Integrated
Circuit
Systems, Inc.
ICSSSTUB32872A
Advance Information
28-Bit Registered Buffer for DDR2
Recommended Application:
Pin Configuration
• DDR2 Memory Modules
123 45 6
• Provides complete DDR DIMM solution with
A
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
B
• Optimized for DDR2 400/533/667 JEDEC 4 Rank
C
VLP DIMMS
D
E
Product Features:
F
• 28-bit 1:1 registered buffer with parity check
G
functionality
H
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
J
• Supports LVCMOS switching levels on RESET input
K
• 50% more dynamic driver strength than standard
L
SSTU32864
M
• Low voltage operation
N
VDD = 1.7V to 1.9V
P
• Available in 96 BGA package
R
T
96 Ball BGA
(Top View)
Functionality Truth Table
In puts
Outputs
RESET DCS0 DCS1 CK
Dn,
CK DODTn, Qn
DCK En
QCS
QODT,
QCKE
H
L
L
↑
↓
L
L
L
L
H
L
L
↑
↓
H
H
L
H
H
L
L
L or H L or H
X
Q₀
Q₀
Q₀
H
L
H
↑
↓
L
L
L
L
H
L
H
↑
↓
H
H
L
H
H
L
H
L or H L or H
X
Q₀
Q₀
Q₀
H
H
L
↑
↓
L
L
H
L
H
H
L
↑
↓
H
H
H
H
H
H
L
L or H L or H
X
Q₀
Q₀
Q₀
H
H
H
↑
↓
L
Q₀
H
L
H
H
H
↑
↓
H
Q₀
H
H
H
H
H
L or H L or H
X
Q₀
Q₀
Q₀
L
X or
X or
X or
X or
X or
floating floating floating floating floating
L
L
L
1222F—3/13/07
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
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